How to simulate PCIE / IEEE path on PCB + Everything you need to know | Explained by Bert Simonovich
Setting up simulation and explaining everything essential you need to know about channel simulation such PCIE or IEEE. Thank you very much Bert Simonovich
Chapters:
- 00:00What is this video about
- 00:53What is channel and why to simulate it
- 06:33Why is loss important
- 14:25Stackup
- 15:21Dielectric properties Df Dk
- 21:47Copper roughness
- 27:34Construction tables and stackup
- 33:0510 layer stackup example
- 38:30When start worrying about stackup details
- 48:03Copper Roughness models
- 57:53Filling up Stackup into Polar software
- 1:03:53Setting up Dk and roughness
- 1:06:46Calculating Loss of a transmission line for stackup in Polar
- 1:09:05Saving model of transmission line
- 1:20:29Creating models of VIAs
- 1:33:20Dielectric anisotropy
- 1:38:52DesignCon
- 1:42:41Creating and setting up simulation
- 1:51:11Simulation and results
- 1:54:04Comparing good and bad PCB material results
- 1:57:28COM - Channel Operating Margin
- 1:59:07Setting up COM simulation
- 2:02:57COM results
