routing 1 data bank in different layers
navid abedi , 03-11-2019, 01:13 PM
hi...i have a question about routing 1 data bank in different layers...
please tell me rules about it.
Best Regards
navid
please tell me rules about it.
Best Regards
navid
Paul van Avesaath , 03-12-2019, 03:46 AM
try and route in groups.. so
CLK, Address and command lines on a single layer or layerpair.
these signals run at half the speed as the rest so you can use multiple layers for it.
datagroups per 8 Bit with the clock of that pair and datamask on a single layer
keep via transmission to a minimum and exaclty the same on each connection
match within 5mil and you are good to go..
if Clock speeds are exceeding 600MHz i would try and match the pin package delay also.
CLK, Address and command lines on a single layer or layerpair.
these signals run at half the speed as the rest so you can use multiple layers for it.
datagroups per 8 Bit with the clock of that pair and datamask on a single layer
keep via transmission to a minimum and exaclty the same on each connection
match within 5mil and you are good to go..
if Clock speeds are exceeding 600MHz i would try and match the pin package delay also.
Comments:
navid abedi, 03-29-2019, 02:40 AM
hi read your comment many times and it helped me alot (:but i can't understand it: if Clock speeds are exceeding 600MHz i would try and match the pin package delay also. what is "pin package delay"??tnx
robertferanec , 03-15-2019, 02:47 AM
I am not exactly sure what you mean, but if you mean routing data signals of same bank different way (e.g. DATA0 routed as L1-L3-L1 and DATA1 routed as L1-L6-L1), than I would not route data signals this way. You can try to length match the signals based on Delay, but in most design you will find signals in one data bank routed the same way.
Paul van Avesaath , 03-29-2019, 02:54 AM
@navid abedi what i mean with this is the following.
if your clock speed of the DDR adres/ctrl lines is 600Mhz, then the datarate is 1200Mhz. if you go to a higher speed lets say a base clock of 1200Mhz you data will go at 2400Mhz (because the data clocks at both flanks of the clock)...
this gives you way tighter margins then @ 600 Mhz.
the internal wirebond length will come into play here so if you have a xilinx FPGA for instance they give the pin package length for each pin. that you can take into account when routing.. meaning that in altium you can add that info into your pin. and xSignal will take that into account. so you will increase your accuracy a lot by doing this.
I have designs were i have done the 600Mhz with just pin to pin matching, so i am confident that it can work. but higher than that it becomes a lot harder..
hope this helps
if your clock speed of the DDR adres/ctrl lines is 600Mhz, then the datarate is 1200Mhz. if you go to a higher speed lets say a base clock of 1200Mhz you data will go at 2400Mhz (because the data clocks at both flanks of the clock)...
this gives you way tighter margins then @ 600 Mhz.
the internal wirebond length will come into play here so if you have a xilinx FPGA for instance they give the pin package length for each pin. that you can take into account when routing.. meaning that in altium you can add that info into your pin. and xSignal will take that into account. so you will increase your accuracy a lot by doing this.
I have designs were i have done the 600Mhz with just pin to pin matching, so i am confident that it can work. but higher than that it becomes a lot harder..
hope this helps
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