DDR3 address/command/control
Luca82 , 05-06-2020, 08:01 AM
Hi,
I'm routing the address/command/control signals of two DDR3.
I'm wondering what is the best strategy.
I'm trying to use the same layer for all of those signals and I'm trying to route the vias from the fanout of the FPGA directly to the vias of the fanout of the 1st DDR3.
In order to have a starting strategy, I tried to identify some "patterns" (see attachment), but event if the drawing looks "easy", the practice is not !
So, would anyone share his strategy or would like to comment mine ?
Thanks a lot !
I'm routing the address/command/control signals of two DDR3.
I'm wondering what is the best strategy.
I'm trying to use the same layer for all of those signals and I'm trying to route the vias from the fanout of the FPGA directly to the vias of the fanout of the 1st DDR3.
In order to have a starting strategy, I tried to identify some "patterns" (see attachment), but event if the drawing looks "easy", the practice is not !
So, would anyone share his strategy or would like to comment mine ?
Thanks a lot !
robertferanec , 05-11-2020, 01:56 AM
Usually you would like to change the layer at least once so you can reorder the signals.
Luca82 , 05-13-2020, 09:28 AM
Hi Robert !
Yes, changing layer once to reorder signals as you did in your OpenRex. I just wanted to try and see if it was possible to do differently, but I could not get good results.
I then decided to go for the same strategy as your OpenRex (as you can see in the picture). I just have to do some length match...
Yes, changing layer once to reorder signals as you did in your OpenRex. I just wanted to try and see if it was possible to do differently, but I could not get good results.
I then decided to go for the same strategy as your OpenRex (as you can see in the picture). I just have to do some length match...
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