FEDEVEL
Platform forum

brs , 01-22-2022, 08:21 AM

Hi, I'm trying to understand delay matched routing and xSignals. I tried some situations and I have four questions.

1. Altium calculates different delays for tracks which are on same layer and have same length but different widths. Why width has effect on delay?
2. How can I calculate via delays?
3. I'm trying to route nets between CPU and LPDDR4. Should I use length matching or delay matching. Tracks of different lenghts can give same delay.
4. I'm trying to implement xSignals on Altium. I created a test project with 2 ICs and a capacitor. I routed basic tracks between 2 IC pads and a capacitor pad. Net's total delay is 193ps and delay between IC pads is 113.9 ps. Lets say it must be 150ps so I created an xSignal between IC pads with min 149ps, max 150ps rule. When I'm trying to tune tracks in NetC1_1_PP1 xSignal with interactive length tuning tool, Altium says "Target Delay Smaller Than Old Delay". Probably it uses total net delay (193ps) instead of xsignal delay. How can I resolve this issue. Please see attached screenshot.

WhoKnewKnows , 01-22-2022, 05:54 PM

Delay is a function of some amount of trace impedance and trace length. Trace width affects trace impedance. I think this should help you with your first question. Perhaps others can help you with the other questions.

robertferanec , 01-25-2022, 10:38 PM

1. can you attach screenshots?
2. I don't know. Normally I route all the signals in group the same way, so it cancels effect of vias. Also, when using xSignals, I think altium now includes delay in VIA
3. It's always delay matching. However many tools can't calculate delay precisely, so length matching is used instead.
4. I don't know why it doesn't work