Altium has not calculate delay for spesific inner layers
maddoxbey , 10-27-2022, 06:02 AM
Hello,
I am using version 20.0.10 and have an issue with delay calculations. For spesific layers in my design delay calculation does not work and stuck at zero ps, not incrementing. I have attached the screenshots. First ss shows the lane, delay shown as 0 for that layer but it works fine for top layer. The other ss shows delays in ps for whole line. Top layer has delays (can check it segment by segment) but this spesific inner layer adds zero delay. (By the way i have other inner layers and they are just work fine.)
I thought this is all about stack up and changed it lots of times but nothing changed. I attached the stack up also.
Can someone please help me about this? I am clueless right now. Is it because some option or ruıle or something? At the moment i have no idea and need enlightment.
Thanks
I am using version 20.0.10 and have an issue with delay calculations. For spesific layers in my design delay calculation does not work and stuck at zero ps, not incrementing. I have attached the screenshots. First ss shows the lane, delay shown as 0 for that layer but it works fine for top layer. The other ss shows delays in ps for whole line. Top layer has delays (can check it segment by segment) but this spesific inner layer adds zero delay. (By the way i have other inner layers and they are just work fine.)
I thought this is all about stack up and changed it lots of times but nothing changed. I attached the stack up also.
Can someone please help me about this? I am clueless right now. Is it because some option or ruıle or something? At the moment i have no idea and need enlightment.
Thanks
robertferanec , 11-02-2022, 08:24 AM
I never trust Altium's length calculations. They keep changing it and it is often broken. We always measure the segments and fill out a spreadsheet which calculates the length.
Comments:
Paul van Avesaath, 12-01-2022, 01:49 AM
i did not either at first but last time i used it i had it checked with hyperlynx simulation it did check out.. even with the length of the internal die pins.. reason i dare to trust it is because i did not put 1 delay in one of the FPGA pins and that stood out like a red flag. so simulation was correct..
WhoKnewKnows , 11-03-2022, 09:04 PM
@robertferanec This seems like maybe a good topic for a YouTube video. Perhaps you could show a few ways the length calculations fail and then demonstrate your spreadsheet method?
robertferanec , 12-05-2022, 03:43 AM
I created one a long time ago: https://www.youtube.com/watch?v=v1EzSt3TfZA PS: xSignals still may help
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