Rule Violations
Satyaveer Singh Rawat , 11-15-2023, 10:36 PM
Hi All, I am getting 252 Rule Violations (83- Silk to Solder Mask and 169- Silk to Silk), some of which are attached in screenshot. Please help me to get-rid of all these violations.
WhoKnewKnows , 11-16-2023, 06:39 AM
Does your PCB design show these errors too, or are the errors only appearing in this list report?
Consider sharing screen shots of your layout.
I suspect there's something about the way the footprints are constructed and your design rules are finding violations within your footprints. It's difficult to say without being able to view your layout.
For every violation listed in the report you shared (that's an HTML report which you can attach as a file instead of screenshot, BTW), there should be a error marker on the layout. This is what you're going to want to screenshot and share when you request help.
Isn't clearing up design rules violations covered in one of your Fedeval Academy classes?
Good luck 🤞
Consider sharing screen shots of your layout.
I suspect there's something about the way the footprints are constructed and your design rules are finding violations within your footprints. It's difficult to say without being able to view your layout.
For every violation listed in the report you shared (that's an HTML report which you can attach as a file instead of screenshot, BTW), there should be a error marker on the layout. This is what you're going to want to screenshot and share when you request help.
Isn't clearing up design rules violations covered in one of your Fedeval Academy classes?
Good luck 🤞
Satyaveer Singh Rawat , 11-16-2023, 09:55 AM
@WhoKnewKnows here is the screenshot of the PCB layout.
For this "Isn't clearing up design rules violations covered in one of your Fedeval Academy classes?".
For me not working perfectly for me. Still trying my best.
For this "Isn't clearing up design rules violations covered in one of your Fedeval Academy classes?".
For me not working perfectly for me. Still trying my best.
qdrives , 11-16-2023, 02:07 PM
1) It shows you that the text "RC0805FR-071ML" is one of them. I another post you were hiding text. This does not allow you to fix the problem. Change the footprint so that that text does not gets placed on the overlay layer.
2) If you find the overlay (silk) data important you need to fix this. If not, you can disable the rule and add a comment to the fabrication documentation that states that the fabricator can strip the overlay data from the soldermask. They may merge or tweak the silk-to-silk errors a bit.
And lastly, zoom in to one of the violations next time. Showing the whole board does not make the violation clear.
2) If you find the overlay (silk) data important you need to fix this. If not, you can disable the rule and add a comment to the fabrication documentation that states that the fabricator can strip the overlay data from the soldermask. They may merge or tweak the silk-to-silk errors a bit.
And lastly, zoom in to one of the violations next time. Showing the whole board does not make the violation clear.
Satyaveer Singh Rawat , 11-17-2023, 12:55 AM
@qdrives, Hi Sir. Sorry but I didn't get your advices apart from this one - "And lastly, zoom in to one of the violations next time. Showing the whole board does not make the violation clear."
Categorically 1. Why 2 points? does it mean that these are the solutions for two Rule Violations 1) Silk to Solder Mask and 2) Silk to Silk?
Here attaching the Screenshot of Resistor Footprint and Schematic . Also the screenshot of complete PCB layout, without handing text as I have done earlier and you suggested that it is wrong method, so I undo that method. Not able to figure out how to hide "RC0805FR-071ML". Please Help.
Categorically 1. Why 2 points? does it mean that these are the solutions for two Rule Violations 1) Silk to Solder Mask and 2) Silk to Silk?
Here attaching the Screenshot of Resistor Footprint and Schematic . Also the screenshot of complete PCB layout, without handing text as I have done earlier and you suggested that it is wrong method, so I undo that method. Not able to figure out how to hide "RC0805FR-071ML". Please Help.
qdrives , 11-17-2023, 03:48 PM
For the previous point 1, here are the steps:
1) Remove the string "RC0805FR-071ML" or place it on another (mechanical) layer.
2) Update all footprints of R0805 in your design by right-clicking the R0805 in the left PCB library navigation and selecting 'Update PCB with R0805'.
3) Select all 'layers' (default) and click ok.
This should update all the footprints on your board and the text "RC0805FR-071ML" should no longer be visible.
Since that text was going over pads and other overlay (silk) items, you got a lot of violations.
Once the violations of the R0805 footprint has been resolved, it is a question how many and to what extend the remaining problems are.
Whenever there are problems within a footprint, it is best to change the footprint itself and update it (see steps of point 1).
You could use the Tools / Silkscreen preparation method for this or manually.
For the last remaining problems there is the question if this would be problematic. I personally do not enable these two rules as it takes too much time fixing the violation and I do not even care much about the silk data anyway.
So yes, just 2 points on the two violation types as they have a common cause/solution.
Point 1 is for fixing most of the issues.
Point 2 is about ignoring the remainder.
1) Remove the string "RC0805FR-071ML" or place it on another (mechanical) layer.
2) Update all footprints of R0805 in your design by right-clicking the R0805 in the left PCB library navigation and selecting 'Update PCB with R0805'.
3) Select all 'layers' (default) and click ok.
This should update all the footprints on your board and the text "RC0805FR-071ML" should no longer be visible.
Since that text was going over pads and other overlay (silk) items, you got a lot of violations.
Once the violations of the R0805 footprint has been resolved, it is a question how many and to what extend the remaining problems are.
Whenever there are problems within a footprint, it is best to change the footprint itself and update it (see steps of point 1).
You could use the Tools / Silkscreen preparation method for this or manually.
For the last remaining problems there is the question if this would be problematic. I personally do not enable these two rules as it takes too much time fixing the violation and I do not even care much about the silk data anyway.
So yes, just 2 points on the two violation types as they have a common cause/solution.
Point 1 is for fixing most of the issues.
Point 2 is about ignoring the remainder.
Satyaveer Singh Rawat , 11-17-2023, 11:53 PM
@qdrives, Thank you very much sir. I followed your instruction and arrives on the stages attached in screenshot. Please guide if:
1) I can ignore these violations and move to next step or
2) Something serious about these violations
3) If 2-Yes, then please explain the steps to mitigate the concern violations.
1) I can ignore these violations and move to next step or
2) Something serious about these violations
3) If 2-Yes, then please explain the steps to mitigate the concern violations.
qdrives , 11-18-2023, 05:36 AM
No you cannot ignore these violations.
Minimum annular rule is set to 0.2mm. This may be decreased to 0.15mm or so, if it is possible for the PCB fabricator. However, this
Hole to hole clearance - I do not see any of them in a quick glance at your design.
Silk to solder mask - see the picture below. The left arrow point to possibly 2 of them. However, the two components are placed to close to each other.
Silk to silk - I see a couple times lines on silk touching other silk lines. You may ignore these (or disable the rule).
Do note that the right arrow above points to a capacitor that is partly mounted off board. Try to keep components away from the edge of the board. A preferred distance is 3...5mm. Now clearly that will be impossible for the USB connector, but you have many on the edge. By default Altium does not have a "board outline clearance". I would add one and set the values as shown below.
I think you can solve all the silk to solder mask violations.
You may ignore (disable) the silk to silk violations. Although, this may be an indication that you place the components to close to each other.
Minimum annular rule is set to 0.2mm. This may be decreased to 0.15mm or so, if it is possible for the PCB fabricator. However, this
Hole to hole clearance - I do not see any of them in a quick glance at your design.
Silk to solder mask - see the picture below. The left arrow point to possibly 2 of them. However, the two components are placed to close to each other.
Silk to silk - I see a couple times lines on silk touching other silk lines. You may ignore these (or disable the rule).
Do note that the right arrow above points to a capacitor that is partly mounted off board. Try to keep components away from the edge of the board. A preferred distance is 3...5mm. Now clearly that will be impossible for the USB connector, but you have many on the edge. By default Altium does not have a "board outline clearance". I would add one and set the values as shown below.
I think you can solve all the silk to solder mask violations.
You may ignore (disable) the silk to silk violations. Although, this may be an indication that you place the components to close to each other.
Satyaveer Singh Rawat , 11-22-2023, 01:42 AM
Dear All, Please help me get out of this (Screenshot attached) as I am finding 121 Rule violations after doing the routing. PCB screenshot also attached herewith. If possible, please tell me the steps to mitigate these violations.
qdrives , 11-22-2023, 04:55 PM
My remarks:
1) Your board shape is not a rectangle
2) You are placing components and traces too close to the board edge
3) When routing, press tab, and set the "interactive routing" properties:
- "Conflict resolution" to "Walkaroud obstacles"
- Check the "Display clearance boundaties"
4) I assume you know how to get rid of the short circuits
5) Net antenna's can be a via that does not connect on 2 or more layers
6) Solder mask sliver, silk to solder mask and silk to silk violations are not so important and can be ignored until the other violations are resolved.
1) Your board shape is not a rectangle
2) You are placing components and traces too close to the board edge
3) When routing, press tab, and set the "interactive routing" properties:
- "Conflict resolution" to "Walkaroud obstacles"
- Check the "Display clearance boundaties"
4) I assume you know how to get rid of the short circuits
5) Net antenna's can be a via that does not connect on 2 or more layers
6) Solder mask sliver, silk to solder mask and silk to silk violations are not so important and can be ignored until the other violations are resolved.
Satyaveer Singh Rawat , 11-25-2023, 11:24 AM
@qdrives Dear Sir, Thank you for your response. Please guide:
1. How to correct the board shape as is distorted at 2 edges?
2. Can I extend the board edges, effectively increasing the board area?
I have tried both of the above points using: Design ---> Board Shape ---> Define Board Cutout (Shown in Screenshot-1) But after doing that my PCB turns in to all Green (Screenshot-2) and when I was not able to get out of it, I have to undo all my actions.
3. I have set all the setting (Walkaroud obstacles etc) as you directed but now my confusion is that do I have to route again because all the routing is done with previous setting. I can understand that new routing i.e. the unrouted nets in rule violation will follow the new setting but what about the older ones. Do I need to do them again?
4. For short circuits: I am not fully confident about correcting all short circuit rule violations. I know what short circuit is and I have followed all the procedure exactly but from where these short circuit rule violations arise I am not aware of.
5. Net antenna's - I have corrected some of them but still handful of them are there.
I know I am being greedy now and asking too much but I want to learn this as I have invested my more than two and half months. So now I don't want to let it go. Please help me in whatever way it is possible.
At present I am having 95 rule violations (From last 121) (Screenshot-3,4 &5) and PCB layout (Screenshot-6).
1. How to correct the board shape as is distorted at 2 edges?
2. Can I extend the board edges, effectively increasing the board area?
I have tried both of the above points using: Design ---> Board Shape ---> Define Board Cutout (Shown in Screenshot-1) But after doing that my PCB turns in to all Green (Screenshot-2) and when I was not able to get out of it, I have to undo all my actions.
3. I have set all the setting (Walkaroud obstacles etc) as you directed but now my confusion is that do I have to route again because all the routing is done with previous setting. I can understand that new routing i.e. the unrouted nets in rule violation will follow the new setting but what about the older ones. Do I need to do them again?
4. For short circuits: I am not fully confident about correcting all short circuit rule violations. I know what short circuit is and I have followed all the procedure exactly but from where these short circuit rule violations arise I am not aware of.
5. Net antenna's - I have corrected some of them but still handful of them are there.
I know I am being greedy now and asking too much but I want to learn this as I have invested my more than two and half months. So now I don't want to let it go. Please help me in whatever way it is possible.
At present I am having 95 rule violations (From last 121) (Screenshot-3,4 &5) and PCB layout (Screenshot-6).
qdrives , 11-26-2023, 01:03 PM
1) My tips:
- Set the grid to a large value (>= 1mm)
- Draw on a mechanical layer the board outline you want. Name this layer the board outline layer. I use mechanical layer for this, but it is up to you which one you choose.
- (In single layer mode) select all the lines and then Design / Board shape / Define board shape from selected objects.
2) Sure, see also point 1.
2a) ...Turns all green (screenshot 2)... --> you have 'removed' the board. If the cut-out has the same shape as the board, you effectively removed the entire board.
2b) Use the Define board shape from selected objects action.
3) No, you do not need to redo nets (track, arcs, etc.) that are ok. But if there are nets that have a short circuit, you have to remove one of the tracks and fix the connection.
4) You might have "drag" enabled for component movement. I do not as Altium creates such shorts. I cannot help you on fixing them as I have too little information about it. The violation will state something like "track on layer x to via". Also make sure that when you double click on the violation that the zoom factor is good enough to be at the location (not to far out / in).
5) See point 4.
When working on the board, just have the top, bottom and top legend layers visible. None of the other layers matter at this time.
- Set the grid to a large value (>= 1mm)
- Draw on a mechanical layer the board outline you want. Name this layer the board outline layer. I use mechanical layer for this, but it is up to you which one you choose.
- (In single layer mode) select all the lines and then Design / Board shape / Define board shape from selected objects.
2) Sure, see also point 1.
2a) ...Turns all green (screenshot 2)... --> you have 'removed' the board. If the cut-out has the same shape as the board, you effectively removed the entire board.
2b) Use the Define board shape from selected objects action.
3) No, you do not need to redo nets (track, arcs, etc.) that are ok. But if there are nets that have a short circuit, you have to remove one of the tracks and fix the connection.
4) You might have "drag" enabled for component movement. I do not as Altium creates such shorts. I cannot help you on fixing them as I have too little information about it. The violation will state something like "track on layer x to via". Also make sure that when you double click on the violation that the zoom factor is good enough to be at the location (not to far out / in).
5) See point 4.
When working on the board, just have the top, bottom and top legend layers visible. None of the other layers matter at this time.
Satyaveer Singh Rawat , 11-28-2023, 04:10 AM
@qdrives and @WhoKnewKnows Dear sir, thank you so much for your continuous support, because of which I am able to remove all the rule violations. I am attaching the current screenshots of the PCB and Design Rule verification Report, Which is showing 6 PCB health Issues. Kindly help me to remove these issues. (step by step, if possible)
qdrives , 11-28-2023, 03:30 PM
"This violation occurs when a footprint model linked to a component being defined in the Component Editor has its reference point (origin) outside of the bounding rectangle formed by footprint objects." -- Offset Footprint Reference
For through hole components, pin 1 is often used as the reference. I assume that it is of you headers (10, 8 and 6 pins) - they do not need to protrude the board edge as the USB connector does. So set the footprint reference to pin 1 and update from the library (these components will move on your board!)
Satyaveer Singh Rawat , 11-29-2023, 10:53 AM
@qdrives Dear Sir, Thank you for your continuous support . I have followed your instructions and found that reference of 3,6,8 and 10 pin headers was outside the rectangle frame of the component. Then I have corrected that in footprint of all the cases. Now what I am getting is that out 6 PCB health Issues, 4 are gone while 2 are still persisting even though I have followed the same process for all the 6 cases. I am attaching following screenshots:
1. Current PCB and Design Rule verification Report
2. 6& 10 Pin Header PCB footprint showing reference inside the rectangle frame (These two giving error)
Kindly guide me what could be the possible error now. I have tried all sort of possibilities as per my knowledge and very surprised that all the errors was exactly same, I have followed the same set of procedure for all 6, 4 of them are eliminated while 2 are still troubling me.
1. Current PCB and Design Rule verification Report
2. 6& 10 Pin Header PCB footprint showing reference inside the rectangle frame (These two giving error)
Kindly guide me what could be the possible error now. I have tried all sort of possibilities as per my knowledge and very surprised that all the errors was exactly same, I have followed the same set of procedure for all 6, 4 of them are eliminated while 2 are still troubling me.
qdrives , 11-29-2023, 02:37 PM
I see that the reference points in the footprint is not perfect in pin 1.
Make sure it snaps correctly to pad centers (Ctrl-E).
On the design you can also show the reference point.
And make sure that you updated the footprint from the library.
Make sure it snaps correctly to pad centers (Ctrl-E).
On the design you can also show the reference point.
And make sure that you updated the footprint from the library.
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