FEDEVEL
Platform forum

Danie , 03-22-2026, 11:44 PM

Hi, I have some noob questions but I want to double check to ease my doubt. My board isn't high frequency or RF or anything, but it is a VERY size constrained board with lots of PWM traces and then some IMU traces etc. I am just trying to get into good habits and have a better understanding of what is important.

1) I have a 4 layer board with the stackup: L1 SIG, L2 GND, L3 POWER & GND, L4 SIG.
If I have signals on layer 4 which I then use a via to briefly route onto layer 1, I understand a stitching via needs to be used. I just want to double check that the adjacent stitching via is definitely meant to be gnd, and not whatever is on the reference plane underneath the trace? So if the layer 4 trace was over the 3V3 plane (layer 3) and I had the layer via, then the adjacent stitching via is gnd, not the 3v3? right? hahaha

2) I have been hesitant to do a polygon pour of GND in the empty spaces on my L1 and L4 of my board, because I saw a video with Eric Bogatin suggesting that people shouldn't just mindlessly do it. I guess I'd like to know if I can be directed to information or anything on why this is the case? Or is it still a good idea to do, as long as I have stitching vias throughout it so that it doesn't have large empty spaces of copper? Or is it only important to have adjacent gnd pours for certain signals?

3) Finally, what exactly dictates the via sizes? I saw in some replies that QDrives asks why some vias are different sizes, and I realised I don't really know the answer.
I would think that for signal traces, the via size is just dependent on the trace size. But then if say I'm trying to create a power plane on layer 4 and I'm using stitching vias for the sake of carrying current, then I don't know how much the via size matters. Because from my understanding, vias, regardless of size, carry ~1A. So in that case, is it more optimal for me to use the smallest via size my manufacturer allows, to try and fit in as many parallel current carrying vias as possible?
But then if I have an IC that draws i.e. 200mA, should my first focus be to create the trace width so that it's wide enough to carry 200mA, and then the via size be based on that trace size?

Thank you!

QDrives , 03-23-2026, 02:30 AM

1) Stitching via cannot be done in that stack-up. You need a capacitor.
2) Pouring the 'signal' layers with copper depends on the design. I have done it for over 80% of my designs. But they are high power and the pour is needed for copper balancing. Otherwise your board bends (I know this from experience).
3) Yes, I do ask questions about via sizes. Not that I have only one size either.
There are many things to be said about via size:
- Aspect ratio is critical. A lower aspect ratio is more reliable to produce. Limit is about 10:1 for through hole.
- Size constraint versus cost. Smaller size is more costly, but you may not have space for big vias. Laser drilled micro vias are even smaller, but also more expensive.
- Filling vias with solder. Well that is only useful when the board is wave soldered (too).
- Current carrying capability. No, the current carrying capability does vary a bit. A simple rule of thumb is 1A per via, but bigger ones (hole >= 0.6mm) can be over 2A per via. The larger space requirement may negate the gain in current compared to multiple smaller ones (0.25mm hole). Then there is the cooling effect of the trace and more importantly, the planes... Science is not fully settled on that one.
- Class 2 or Class 3. But that is more on the pad size than the hole, although class 3 does limit the aspect ratio to 8:1.
- Annular ring minimum and do not forget that the drill used to make the via may be bigger then the size you have in the design. The bigger the annular ring, the more reliable the production, but the more space you need.
In most cases you can simply use a single size via that fits your size, cost and reliability requirements.

Danie , 03-23-2026, 03:36 AM

Thanks so much for your response - lot's of stuff for me to look further into.
Do you have any recommended resources where I can read into more detail about the stitching capacitors? I can only seem to find reddit posts and stack exchange content, and when it was mentioned it was about crossing a plane split.
If my entire trace on the bottom layer was routed above the 3V3 plane and then I'm briefly routing over the top layer, (which I guess the layer underneath is now ground), does this still count as a plane split and need the capacitor?

QDrives , 03-23-2026, 07:49 PM

I think there may be a Rick Hartley video that tells you to use a capacitor, but I have done the paid training from him where it may have been.
As for the small change... there is no hard rule that if you omit the capacitor it will fail (functionally or EMC).
It depends on many things (e.g. rise time), but if the start and end is both on the bottom layer, I think the problem is a lot less then when it starts on the bottom and ends on the top.