How does one determine the track width for "slow" signals?
gyuunyuu1989 , 04-11-2023, 04:22 PM
For signals that are "high speed" signals, the track width is a function of the distance from the ground and required characteristic impedance.
However, for other tracks that carry signals that do not fall into the "high speed" category, how does one determine what track width to use? There are so many different packages with different pad spacing and pad size, so I am not sure if "one width fits all" is possible. Also, I am sure that there will be a rule of thumb regarding the track widths. Also, when we talk about track width, the track spacing is also relevant.
Now, coming to the power supply. We could have power supply spread using power planes in the PCB. Is this how it must always be done? What if we use PCB tracks with decoupling capacitors to ground and not use any power planes at all? If it is ok to use PCB tracks for power supply rails, how do we know how wide they must be?
However, for other tracks that carry signals that do not fall into the "high speed" category, how does one determine what track width to use? There are so many different packages with different pad spacing and pad size, so I am not sure if "one width fits all" is possible. Also, I am sure that there will be a rule of thumb regarding the track widths. Also, when we talk about track width, the track spacing is also relevant.
Now, coming to the power supply. We could have power supply spread using power planes in the PCB. Is this how it must always be done? What if we use PCB tracks with decoupling capacitors to ground and not use any power planes at all? If it is ok to use PCB tracks for power supply rails, how do we know how wide they must be?
gyuunyuu1989 , 04-12-2023, 10:34 AM
OK, lets take some examples.
1. FPGA BGA pad connects to SPI slave SOIC pad. Both are 3.3V.
2. MCU QFP pad connects to edge connector where the edge connector. Signal is differential 1.2V.
3. FPGA BGA pad connects through resistor to LED that is grounded. The FPGA buffer drives 5V (for sake of argument).
Only in the 3rd case can one know how much current is going to be source/sink through the PCB track. In the first two cases, the current will source/sink when the logic level is changing and then stop (except leakage current). How does one determine the current amount or using some alternate method, the correct track width to use?
Lets say you are putting design rules into PCB design software for these tracks. What design rule would you enter? Or alternatively, if an intern that never designed PCB before came and asked these questions, what figure would you give them?
1. FPGA BGA pad connects to SPI slave SOIC pad. Both are 3.3V.
2. MCU QFP pad connects to edge connector where the edge connector. Signal is differential 1.2V.
3. FPGA BGA pad connects through resistor to LED that is grounded. The FPGA buffer drives 5V (for sake of argument).
Only in the 3rd case can one know how much current is going to be source/sink through the PCB track. In the first two cases, the current will source/sink when the logic level is changing and then stop (except leakage current). How does one determine the current amount or using some alternate method, the correct track width to use?
Lets say you are putting design rules into PCB design software for these tracks. What design rule would you enter? Or alternatively, if an intern that never designed PCB before came and asked these questions, what figure would you give them?
Comments:
Paul van Avesaath, 04-12-2023, 01:20 PM
ok so what i would do is spi -> 6-10 mill depending on how much room you haveMCU QFP -> 6-10 mill depending room and if you need a impedance controlled line,FPGA to LED or a power trace. 10 - 20 mill depending on room.you wil be suprised how much power can go trrough a 6 mil trace round 0.85A so you are not really in trouble power wise..usually the thinner the traces the more expensive the board.. most manufacturers are pretty comfortable with 6 mil traces, via's of 18/8 mil or 24/12 mil.. and that will get you trough most designs..better to use one width and one via type on a board if you can manage.. this will make the board cheaper to produce.if you or an intern is just starting out, use rules from previous designs or grab the rules from a webiste like https://jlcpcb.com/capabilities/pcb-capabilitiesthose are the easy ones to find.. you will tune them around the feedback you get from EMS or PCB manufacturers, but it is a great way to start.
Paul van Avesaath , 04-12-2023, 08:10 AM
track sizes (as with via's) for "slow signals is not like a rule.. again depending on how much power you want to push true the trace.. use the saturn pcb toolkit to determine what is optimal.. but be aware of making tracks to thick when connecting 0402, if you connect to much thermal mass to one end of a component it can cause issues with production. for power supplies i usually take track widths as wide as the connection pad. and use as much polygon planes as possible.. as example:
please note that i havent poured the power plane yet in the above case..
or something more heavy duty
please note that i havent poured the power plane yet in the above case..
or something more heavy duty
gyuunyuu1989 , 04-12-2023, 10:34 AM
OK, lets take some examples.
1. FPGA BGA pad connects to SPI slave SOIC pad. Both are 3.3V.
2. MCU QFP pad connects to edge connector where the edge connector. Signal is differential 1.2V.
3. FPGA BGA pad connects through resistor to LED that is grounded. The FPGA buffer drives 5V (for sake of argument).
Only in the 3rd case can one know how much current is going to be source/sink through the PCB track. In the first two cases, the current will source/sink when the logic level is changing and then stop (except leakage current). How does one determine the current amount or using some alternate method, the correct track width to use?
Lets say you are putting design rules into PCB design software for these tracks. What design rule would you enter? Or alternatively, if an intern that never designed PCB before came and asked these questions, what figure would you give them?
1. FPGA BGA pad connects to SPI slave SOIC pad. Both are 3.3V.
2. MCU QFP pad connects to edge connector where the edge connector. Signal is differential 1.2V.
3. FPGA BGA pad connects through resistor to LED that is grounded. The FPGA buffer drives 5V (for sake of argument).
Only in the 3rd case can one know how much current is going to be source/sink through the PCB track. In the first two cases, the current will source/sink when the logic level is changing and then stop (except leakage current). How does one determine the current amount or using some alternate method, the correct track width to use?
Lets say you are putting design rules into PCB design software for these tracks. What design rule would you enter? Or alternatively, if an intern that never designed PCB before came and asked these questions, what figure would you give them?
Comments:
Paul van Avesaath, 04-12-2023, 01:20 PM
ok so what i would do is spi -> 6-10 mill depending on how much room you haveMCU QFP -> 6-10 mill depending room and if you need a impedance controlled line,FPGA to LED or a power trace. 10 - 20 mill depending on room.you wil be suprised how much power can go trrough a 6 mil trace round 0.85A so you are not really in trouble power wise..usually the thinner the traces the more expensive the board.. most manufacturers are pretty comfortable with 6 mil traces, via's of 18/8 mil or 24/12 mil.. and that will get you trough most designs..better to use one width and one via type on a board if you can manage.. this will make the board cheaper to produce.if you or an intern is just starting out, use rules from previous designs or grab the rules from a webiste like https://jlcpcb.com/capabilities/pcb-capabilitiesthose are the easy ones to find.. you will tune them around the feedback you get from EMS or PCB manufacturers, but it is a great way to start.
qdrives , 04-12-2023, 12:50 PM
The width, and more specific, the minimum width is also determined by the copper thickness.
Thicker copper needs wider traces.
Thicker copper needs wider traces.
robertferanec , 04-18-2023, 07:19 AM
- signal track width: For cheap PCBs I start with 10mils / 0.254mm or if needed I go down to 6 mils / 0.15mm. For more complex PCBs and inner layers I use 4mils / 0.1mm. Then, once the PCB is finished, based on stackup I will make all these tracks narrower to meet 50OHM impedance. Usually the final width is between 6 - 3 mils. I do this for all digital signal tracks, it's not important if they are "high speed" or not. However I may generally make analog signals wider, e.g. 20 or 40 mils (0.5 or 1mm)
- powers: you really would like to have solid GND plane, but power tracks may be used instead of polygons. This video may help: Do You Really Need Power Planes? Are you sure? | Eric Bogatin https://youtu.be/kdCJxdR7L_I
- powers: you really would like to have solid GND plane, but power tracks may be used instead of polygons. This video may help: Do You Really Need Power Planes? Are you sure? | Eric Bogatin https://youtu.be/kdCJxdR7L_I
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