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chathurayasasvi , 10-10-2024, 06:15 AM

1. Impedance Calculation Discrepancy in KiCad and JLCPCB Tools:

The impedance calculators in KiCad and JLCPCB’s tool give me different trace widths for the same target impedance (e.g., 90Ω differential). I’ve attached a screenshot showing the differences. Why do the results differ between these tools, and which value should I trust for routing? What adjustments might be needed?

2. Coplanar vs. Non-Coplanar Differential Pairs in KiCad:

I’m using a 4-layer PCB with microstrip line routing for differential pairs. The reference plane is on Layer 2 (Ground), and there’s also a ground plane on the top layer. I want to use non-coplanar routing, but I’m concerned that the ground plane on the top layer is too close, possibly making it behave like a coplanar differential line.

Is there a specific clearance needed to ensure non-coplanar routing in this setup? Additionally, why doesn’t KiCad support coplanar differential pairs directly?

3. Clearance Guidelines for Differential Pairs:

Is my method of maintaining the clearance between differential pairs and the ground plane at least three times the trace width correct? Should the same rule apply to pair-to-pair clearance? If not, what’s the usual recommended clearance for pair-to-pair spacing and differential pair-to-ground clearance to ensure good signal integrity?

4. Layer Switching and Impedance Control:

In my 4-layer PCB, the stack-up is signal + ground, ground, power, and signal + ground. I’m routing differential pairs on the top layer, referenced to the ground plane (Layer 2), but due to space constraints, I need to route some pairs on the bottom layer.
How do I ensure consistent impedance when switching layers? Should I use via stitching to maintain the ground reference or place capacitor stitching when changing layers to preserve signal integrity? I also follow the 3W rule for pair-to-pair clearance and differential pair-to-ground clearance. Is this a correct approach for maintaining signal integrity?

QDrives , 10-10-2024, 07:51 PM

1) Where does your KiCad Er value (4.5) come from?
3) You mean the clearance between pairs or other traces being 3 times the height from the return plane? (language, which drives which)
In a sense you want all signal traces, except within a pair, to be as far away as possible. However, some simple rules like 3W, 7H, etc. are to have the cross talk reduce to less than 5%.
2) That could also be why JLCPCB has the trace narrower than KiCad as it will reduce the width a little bit.
4) As L3 is power you need a capacitor when you switch L1 to L4. Question is: do you need a power plane?

chathurayasasvi , 10-13-2024, 03:07 AM

@QDrives
1) I used the default value. In jlcpcb it is 4.4 ( My assumption was 0.1 won't do anything ).

3) No. For an example, if my differential pair width is 0.25 mm i used the clearance as 0.75 mm.( 3 x width ) When i put copper pour on top layer, i used 0.75 mm clearance for it. My mother tongue is not English so i am sorry if i was not clear enough.

Can you guide me to how to put Clearance because i am confused. Simply i want to know
1) how much clearance should i maintain between diff pair to another diff pair
2) If i have a copper pour ,
diff pair to copper pour clearance
3) single ended trace to another single ended trace
4) single ended trace to copper pour

4) Yeah it is a 3.3V power plane , I need a power plain because i have so many components that use 3.3V. I used poe to get 5V then i have boost convert to generate 12V. And most of the sensors powered from 3.3V because my logic levels are 3.3V based.
Can i have a little ground pour inside of power plane ?

chathurayasasvi , 10-13-2024, 03:10 AM

QDrives , 10-13-2024, 07:49 PM

3.1, 3.2, 3.3 and 3.4 are all the same clearance. And you can use your 3W rule for that.

4) It is often not so much the amount of components powered from a rail that drives the use of power planes, but the amount of current through them.
But yes, you can place another pour net in there as long as no trace crosses the gap.