FEDEVEL
Platform forum

PMICnewbie , 02-06-2025, 04:38 AM

In the lesson nets reveal that the inductor is connected with +1V5 however in the schematic it does not, how do I solve such issues and future issues where things in the schematic and layout dont match whats in the lesson. @Robert Feranec , Sometimes it becomes frustrating.

Robert Feranec , 02-06-2025, 07:42 AM

there may be a short circuit in your schematic, I would double check that.

Are you using 100 or 50 mil grid in schematic? that is very important. Looking at your schematic it looks like you don't use snapping to grid and that may cause a lot of problems with wrongly connected / not connected nets.

PMICnewbie , 02-08-2025, 10:00 PM

Thanks, so I snap to grid for both options now, I dont know these settings 100 or 50 mil grid, acrually snapping to grid in both options made it moere cumbersome but Ill turn that option for future ORCAD schematics

PMICnewbie , 02-08-2025, 10:09 PM

And yes there was a missing connection when I checkd the datsheet that explains the missing rats in the layout

PMICnewbie , 02-08-2025, 10:26 PM

Another Side question , everything I change the width of w, its very bad that it hides the adjacent layer as if its gone while Im routing , if you see in the image I was routing the vref3 pin , and it hid the +Vin pin, just to get a snapshot there was an angle at which I had to go around, but it does that even for a small distance in between tracks it hides the adjacent one

PMICnewbie , 02-08-2025, 10:40 PM

Basically I asked before as well, There is a very unexpected frustrating thing happening in
when I try to connect and start tracks from the pins, they miss the connections and try to show tracks around the components rather that on them, but when I start from the end of the component itself to the pin it sorta connects, note I am using different track widths and changing them mid pathway, @QDrives answered that I route backwards from the component to the pin but there might ne another issue @Robert Feranec of why my tracks dont connect in between the 0.5 and 0.2 tracks

PMICnewbie , 02-08-2025, 10:42 PM

I had to go all the way from the capacitor back to the pin rather than from the pin to the capacitor

QDrives , 02-08-2025, 10:42 PM

I just gave that comment as sometimes in Altium it work that way.
I have never worked with Alegro so cannot tell much.

PMICnewbie , 02-09-2025, 06:11 PM

@Robert Feranec Apologies for bombarding with so many queries but as you can see I have more DRC than in your lesson But I believe I can probably solve than in Lect 10 "Improving Layout", but you can see how the pin in the right is hiffen and not connected despite connection being there. I did the rest of the bottom side layout correctly

PMICnewbie , 02-10-2025, 03:36 AM

Could it be possible due to the line width? On Layer 3, 1 mm wide net that was very wide as per instruction didnt connect while 0.2 mm connected, some settings are messed up and I cant figure it out

Robert Feranec , 02-10-2025, 07:42 AM

just continue and you can start clearing the DRC after you connect everything

PMICnewbie , 02-10-2025, 08:32 AM

thanks it was very hard but worth it

PMICnewbie , 02-10-2025, 08:33 AM

Also in the lesson you dont get these DRC errors,I get these fiducial errors and unable to fix them wondering how do I do it

Robert Feranec , 02-10-2025, 11:49 AM

looks like you have them on the top of each other - are they on top and bottom side?

PMICnewbie , 02-10-2025, 04:10 PM

Yes you are right when I hover for info over them, both are on top layer and I guess on top of each other, how do I fix this, I have only 4 overall fiducials, if I remember from the lesson they were four in each corner. do i change the layer of the other four or move them away?

PMICnewbie , 02-10-2025, 04:17 PM

when I move it its only one circle unfortunately,how do i seperate them

PMICnewbie , 02-10-2025, 04:38 PM

Robert Feranec , 02-10-2025, 04:46 PM

I dont have allegro installed, but you should be able to select it as a component and then place on bottom. did you try it in component / placement mode?

PMICnewbie , 02-10-2025, 08:46 PM

I found something interesting, its a spacing issue within the .dra file, thats whats appearing in the layout itself

PMICnewbie , 02-10-2025, 08:50 PM

there were two shapes defined over one another, Im learning to debug from the lessons after going back, thanks @Robert Feranec