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Cyclone IV E - Can't Find Impedance
jpartis1 , 06-18-2018, 10:18 AM
I'm developing a custom control board based on the Cyclone IV E board, and started with the DE2-115 board so my design is based around the same components.
I can't seem to find a document which clearly states the output driver impedance, or input impedance for single ended as well as differential pairs.
I would really appreciate if someone could help me with this I would truly appreciate it.
I can't seem to find a document which clearly states the output driver impedance, or input impedance for single ended as well as differential pairs.
I would really appreciate if someone could help me with this I would truly appreciate it.
robertferanec , 06-20-2018, 03:49 AM
In some chips you can play with the pin parameters, so there is no specific table for output impedance. This is what I found in this document:
https://www.altera.com/en_US/pdfs/li...cyiv-53001.pdf
"Cyclone IV devices feature OCT to provide I/O impedance matching and termination capabilities. OCT helps prevent reflections and maintain signal integrity while minimizing the need for external resistors in high pin-count ball grid array (BGA) packages. Cyclone IV devices provide I/O driver on-chip impedance matching and RS OCT for single-ended outputs and bidirectional pins. "
What I would do, I would use the standard impedances for layout (e.g. google for "Com Express Design Guide", page 182: https://www.picmg.org/wp-content/upl...013-12-061.pdf ) or the impedances required by the chips / interfaces you are connecting to the FPGA. However, before I would start doing layout, I would try to understand how to set the FPGA pin parameters to meet the selected impedances.
https://www.altera.com/en_US/pdfs/li...cyiv-53001.pdf
"Cyclone IV devices feature OCT to provide I/O impedance matching and termination capabilities. OCT helps prevent reflections and maintain signal integrity while minimizing the need for external resistors in high pin-count ball grid array (BGA) packages. Cyclone IV devices provide I/O driver on-chip impedance matching and RS OCT for single-ended outputs and bidirectional pins. "
What I would do, I would use the standard impedances for layout (e.g. google for "Com Express Design Guide", page 182: https://www.picmg.org/wp-content/upl...013-12-061.pdf ) or the impedances required by the chips / interfaces you are connecting to the FPGA. However, before I would start doing layout, I would try to understand how to set the FPGA pin parameters to meet the selected impedances.
jpartis1 , 07-19-2018, 08:06 AM
Hi Robert!
Thank you for that reply, it helps clear some things up in my mind.
Unfortunately, the OCT on the Cyclone IV E doesn't seem to support 3.3V LVTTL, which is what is required for the SDRAM (IS42S16320F-6TLI).
That would been a wonderful option to have, but after searching through many documents, I was disappointed OCT isn't supported in my configuration (I could be wrong).
I do know that the pin drive strength can be adjusted though, and that may help with matching.
I spoke with I very nice representative over at ISSI, and they informed me that 50-60ohm was a popular recommendation from many controller's vendors (including Altera) with SDRAM.
He went on further to say that the drive strength of the SDRAM is typically in the range of 30ohm, which is stronger than the 50-60ohm impedance of the transmission line, and can cause signal reflections, therefore, they recommend ~20ohm serial termination on the transmitter.
The issue is, on the bi-directional data lines, both the FPGA & SDRAM will be driving at different times.
QUESTION 1:
How do you position the series terminators in this case?
ISSI recommends placing the resistors in the "middle", which makes sense.
QUESTION 2:
do you agree with this?
On a side note, I found your 12 layer stackup and noticed that it contains uVias for only signal layer 1 & 2 to ground plane between them, but not to signal layer 3, and same on bottom.
I was wondering how you use the uVias in your routing.
QUESTION 3:
Can you please explain how your architect your layers, ie, what goes on what layer?
Do you use uVias to make ground connections, to internal plane, or do you use through hole vias for this?
Would you please elaborate on these so that I can get a clear understanding, and so that I will be better able to select the proper uVias, stackup layers, etc.
Thank you!!
Thank you for that reply, it helps clear some things up in my mind.
Unfortunately, the OCT on the Cyclone IV E doesn't seem to support 3.3V LVTTL, which is what is required for the SDRAM (IS42S16320F-6TLI).
That would been a wonderful option to have, but after searching through many documents, I was disappointed OCT isn't supported in my configuration (I could be wrong).
I do know that the pin drive strength can be adjusted though, and that may help with matching.
I spoke with I very nice representative over at ISSI, and they informed me that 50-60ohm was a popular recommendation from many controller's vendors (including Altera) with SDRAM.
He went on further to say that the drive strength of the SDRAM is typically in the range of 30ohm, which is stronger than the 50-60ohm impedance of the transmission line, and can cause signal reflections, therefore, they recommend ~20ohm serial termination on the transmitter.
The issue is, on the bi-directional data lines, both the FPGA & SDRAM will be driving at different times.
QUESTION 1:
How do you position the series terminators in this case?
ISSI recommends placing the resistors in the "middle", which makes sense.
QUESTION 2:
do you agree with this?
On a side note, I found your 12 layer stackup and noticed that it contains uVias for only signal layer 1 & 2 to ground plane between them, but not to signal layer 3, and same on bottom.
I was wondering how you use the uVias in your routing.
QUESTION 3:
Can you please explain how your architect your layers, ie, what goes on what layer?
Do you use uVias to make ground connections, to internal plane, or do you use through hole vias for this?
Would you please elaborate on these so that I can get a clear understanding, and so that I will be better able to select the proper uVias, stackup layers, etc.
Thank you!!
robertferanec , 07-24-2018, 01:41 AM
1) Simple answer - middle and simulate. Longer answer: Search this forum for "SDRAM", that can help you. Here is one document from one of the discussions:
2) the uVIAs in our designs go between 1-2 and 2-3. Simple answer: we use it this way, because we can use smaller uVIAs. Long answer: search for "via aspect ratio". Again you can find some thing on this forum e.g. here: http://www.fedevel.com/designhelp/fo...vs-trace-width
3) I only use through hole VIAs for power pins (there may be exception when you can use fileld uVIA to connect power). About layer planning, this may help: https://www.fedevel.com/welldoneblog...should-we-use/
2) the uVIAs in our designs go between 1-2 and 2-3. Simple answer: we use it this way, because we can use smaller uVIAs. Long answer: search for "via aspect ratio". Again you can find some thing on this forum e.g. here: http://www.fedevel.com/designhelp/fo...vs-trace-width
3) I only use through hole VIAs for power pins (there may be exception when you can use fileld uVIA to connect power). About layer planning, this may help: https://www.fedevel.com/welldoneblog...should-we-use/
jpartis1 , 07-24-2018, 07:47 AM
Hi Robert,
Thank you! That was exactly what I was looking for!!
As usual, you are always very helpful and the information you provide is on target.
Regards,
John
Thank you! That was exactly what I was looking for!!
As usual, you are always very helpful and the information you provide is on target.
Regards,
John
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