FEDEVEL
Platform forum

, 03-19-2026, 09:47 PM

Hello,
In my design I am using non-coplanar diff impedance. But I would like to pour GND polygon around and leave enough clearance between USB traces and polygon edge. In the sense that it will still be non-coplanar and the GND polygon will not affect the diff impedance. Is this good idea? Or you not recommend to use GND polygon anymore, since this board is 6 layer? And I must rather connect all the GND pads using the vias?
L1-signal+some power lines,
L2-GND plane,
L3-signal,
L4-PWR,
L5-GNDplane,
L6-signal+some power lines

Refer to attached picture. My current idea with GND polygon.

One more question:
In this post, I got advice how to work with length matching - https://discord.com/channels/1119543365546029098/1478688886275178647
I would like to ask about the gap between different diff pairs (for example SSTX vs SSRX). I followed rules from this app note, section 3.6.5.2 - https://ww1.microchip.com/downloads/en/AppNotes/00001876.pdf
So, my trace width is 7.1mil*5 = 35mil -> I use gap 40mil. Check the attached picture with dimension.
My question is:
With pink, I marked the distance 40mil and one length tuning "hill". Is it acceptable to do it like I drew? Then the distance "green dimension" is less than "5 times trace width".
Or do I have to move the diff pairs apart individually so that the green dimension is 40mil?

Thank you.
Best regards,
Martin

QDrives , 03-20-2026, 04:47 PM

Flooding top, bottom or other layers with copper is a copper balancing thing.
Make sure you have about the same amount of copper in the stack symmetry. If I look at your picture with the cyan floods, you are not applying a copper balance.
An inbalance in copper can make the board bend.

As for the trace spacing, the app note just mentions 3x and 5x. 3x would be about the minimum. >5x is optimal.
For the length tuning sections it would not be a big problem going below 5x for a bit.
I assume the dielectric height is less than 7.1mil?

, 03-20-2026, 07:39 PM

Hello Qdrives,
Thank you for feedback about polygon pour.

Yes, the dielectric height is less than 7.1mil. I am using attached stackup and the dielectric height is 3.91mil, right?

Martin

, 03-20-2026, 08:00 PM

Also, one more question about tie copper balancing. So, you recommend me to delete the copper pours on the top and rather connect the GND pads using the vias?

QDrives , 03-20-2026, 10:10 PM

So if you consider that your spacing is less than 5x 3.91 mill ~ 20mil, and more than 3x7.1mil ~21mil, you should be ok.

QDrives , 03-20-2026, 10:14 PM

Top is red, right? And cyan? Or is that Gnd (net color)?
For the top and bottom you may want to look into this:
https://www.eurocircuits.com/platingindex-_solutions/

, 03-21-2026, 06:03 AM

Sorry for not clear info in my previous post. TOP is red and cyan is only the net color.

, 03-21-2026, 06:55 PM

Hi QDrives,
Thank you for the link, its teachable. So, I deleted the polygon pour from the TOP. But, I am thinking about bottom. On the bottom I have only few short usb data lines routed. So, I did this:
- I set 100mil clearance between GND polygon pour and USB data lines to avoid some interference between them and have "stable" non-coplanar diff impedance. Is this good way?

Or do you recommend to set the clearance bigger?

Otherwise, the polygon is nicely pour out over the entire dps except for the highlited places in the picture.

Thank, Martin

QDrives , 03-22-2026, 05:13 PM

If you put a polygon on the bottom, you better also put one on the top.
You need to balance the copper in the stack (symmetry) otherwise your board will bend / twist (speaking from experience).

As for the clearance -- might as well reduce the clearance and take into the calculation.

, 03-22-2026, 05:45 PM

Okay, I understand.
Can you explain me how you mean the statement "might as well reduce the clearance and take into the calculation"? How to calculate? You mean with this, that I will calculate diff impedance as coplanar?
I heard/read or somebody told me that using non-coplanar is better...

QDrives , 03-22-2026, 09:59 PM

It is a "grounded co-planar wave guide". You still have Gnd below it.
In Altium (Simbeor) the clearance of the co-planar does not seem to have a significant efffect.

, 03-23-2026, 10:08 AM

Yes, for TOP I have the GND plane still in L2 and for BOTT I have the GND plane above in L5.

Sorry but this statement "In Altium (Simbeor) the clearance of the co-planar does not seem to have a significant effect." is not clear for me. What do you want to say with it?

I understand it this way:
You want to say that I can pour GND polygon around USB traces on the TOP and BOTT with much smaller clearance gap than 100mil which I sent in the preview picture (BOTT layer)? But when I check the JLCPCB impedance calculator, the width/gap for non-coplanar vs coplanar return slightly different values.

Thanks, Martin

QDrives , 03-23-2026, 07:59 PM

The calculator here: https://jlcpcb.com/pcb-impedance-calculator/
Setup: see screenshot
Trace width non co-planar: 4.8800 mil
Trace width co-planar: 4.7900 mil
So 0.09 mil difference... that is less then the production tolerance I would say.
So any clearance greater then the trace spacing would be good enough.