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Power plane polygon pours
FuzzyOtter , 02-16-2024, 08:02 PM
Hi friends, still somewhat new to the game, and have a few questions about routing. I am working on a 2-layer board design that includes a buck converter (LMR51606, 1.1MHz, 14V in, 5V out). I have placed and routed the components taking some design cues from the datasheet. I have laid a polygon pour for the incoming power (net INT_Vss), and for the switching node. My questions are:
1) Should I lay an small polygon pour for GND connections around the buck converter now, or should I wait until I add the top and bottom layer pour (both of which will be GND) and review it to make sure there is sufficient GND connection then? In the attached, I have shown the routing with a top layer GND pour.
2) Are thermal reliefs around the pads of devices connected to a GND pour detrimental in this kind of application? I can't imagine the inductance is high enough to be significant, but I see many designs do not include them and simply directly connect, so I need to do some research here.
3) Open to suggestions/feedback about the layout in general. I might be worrying about nothing, or perhaps I'm missing a bigger picture. Only 2 or 3 of these will be made for a personal project, but I'd like to learn as much as I can along the way.
1) Should I lay an small polygon pour for GND connections around the buck converter now, or should I wait until I add the top and bottom layer pour (both of which will be GND) and review it to make sure there is sufficient GND connection then? In the attached, I have shown the routing with a top layer GND pour.
2) Are thermal reliefs around the pads of devices connected to a GND pour detrimental in this kind of application? I can't imagine the inductance is high enough to be significant, but I see many designs do not include them and simply directly connect, so I need to do some research here.
3) Open to suggestions/feedback about the layout in general. I might be worrying about nothing, or perhaps I'm missing a bigger picture. Only 2 or 3 of these will be made for a personal project, but I'd like to learn as much as I can along the way.
corlas , 02-17-2024, 09:45 AM
1. I think it's application specific, but in this case a large polygon at the end of the design is better.
2. Usually it's better to do a solid connection, but it's worse to solder it.
3. I think this layout is fine. Just change the vias to tented vias so they are covered by the mask.
2. Usually it's better to do a solid connection, but it's worse to solder it.
3. I think this layout is fine. Just change the vias to tented vias so they are covered by the mask.
QDrives , 02-17-2024, 03:40 PM
Thermal relief becomes more important for thicker copper and manually (de)soldering.
However, I have never had problems with adding thermal reliefs.
However, I have never had problems with adding thermal reliefs.
Robert Feranec , 02-18-2024, 11:16 AM
I would probably place C6 and C7 very close to the L1 pin and I would probably route the Vin to both pins.
Roomi#0787 , 02-20-2024, 03:39 AM
I prefer without thermals specially for the inductors and controller chip as it helps a bit in heat dissipation
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