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sam , 04-18-2025, 07:40 PM

Hi Phill and anyeone else out here..

In your DDR3 routing video from advanced hardware design course, you mentioned that there are two options for delay matching. You mentioned that either of these two will work the same but I don't understand how.
I understood #Option1 method and that is what I've implemented. Buw now that I revisited video, then I got confused.

#Option1
1) Create xSignals from controller to 1st Memory and have them delay matching
2) Create xSignals from controller to 2nd Memory and have them delay matching

#Option2
1) Create xSignals from controller to 1st Memory and have them delay matching (same as #Option1)
2) Create xSignals from 1st Memory to 2nd Memory and have them delay matching

Below are my questions,
1) Can you confirm that you are not taking account of stubs created between its vias and 1st Memory when you match delay in step 2) for #Option1? so signals from controller are "touching vias (not going through)" then straight to 2st memory?
2) How dose step 2) in #Option2 work? Signals from controller to the vias (connections or stubs just before hitting 1st Memory's pads) are different and also these stubs created between its vias and 1st memory are also different as total delays from controller to 1st memory is what matters.
So doesn't this mean that delay seen by the controller to 2nd Memory will be different even though you have matching delays from 1st memory to 2nd memory? Address, clk, control signals are coming from controller right? I guess it won't matter if via-in pad are used but example you had was dog-bone fan out and I followed that as well.

I finished routing by following #Option1 🙂, hoping that I didn't scerw up as it took so much time haha.. If somehting is not clear, please let me know as well. I will provide images of routing or anything if it helps.

Thank you

Regards,
Sam