FEDEVEL
Platform forum

Susano , 04-07-2026, 08:28 PM

I know the gold standard is Signal-Gnd-Gnd-Signal for 4 layer board but I'm wondering why everyone is debating about stackups like
1- Sig-Gnd-Pwr-Sig
2- Sig-Gnd-Sig-Pwr
3- Sig-Gnd-Gnd-Sig

I know we have to be careful with replacing the inner planes with pwr because of the signal to gnd plane thickness is different between L1 and 2 and L1 and 3 and the splits in the power plane

but I was wondering why not just pour my bottom layer with Power too ?
I mean what are the cons of sharing the bottom layer between signal and pwr in other words (Sig/Gnd pour-Gnd-Gnd-Signal/Pwr pour) keeping in mind a 3x Dielectric thickness of clearance or more of course to reserve the non coplanar impedance

Robert Feranec , 04-08-2026, 06:06 AM

if i have two GND inside I use sig + pwr outside

Susano , 04-08-2026, 12:29 PM

I'm routing pwr on L1 and L4 anyway but the idea was instead of pouring the exceess space on top and bottom to Gnd like usual
what about pouring L4 with PWR instead this would make the top layer much cleaner for signal routing I don't see it used often though

most people route power and just pour gnd for the excess space on top and bottom layer so I'm wondering why what are the tradeoffs

QDrives , 04-08-2026, 03:50 PM

First question is what speeds are we talking (rising edge times)?

The problem with power as a plane is getting the return energy back to the source.
If the power plane is 3.3V and your sources uses that 3.3V power to drive the signal, then there is not problem.
However, if your source uses another power source, then you need the return energy to somehow return to the source. That is through capacitors.

When pouring the bottom layer, you should also pour to the top layer to balance the copper. If you don't, your baord may bend.
Same goes for inner layers (e.g. Sig - Gnd - Sig - Gnd).

Susano , 04-08-2026, 08:21 PM

I'm talking about signals of 5 ns and less

I know your point about referencing plane however L1 and L4 signals would be referencing L2 and L3 gnd planes so it shouldn't be a problem to pour L4 with 3.3V and route some signals on the same layer right ? assuming I keep enough coplanar clearance of course ?
if so why don't I see this often

QDrives , 04-09-2026, 12:13 AM

"*if so why don't I see this often*" -- Because most designers just copy. Copy from other designers, other designs or people like Eric Bogatin.

And no, it is not a problem to pour 3.3V on L4... except: you need to balance copper, so you may also need to pour on L1.

Robert Feranec , 04-09-2026, 05:46 AM

This video can also help: https://youtu.be/kdCJxdR7L_I

Susano , 04-10-2026, 01:03 AM

I first wanna say I really appreciate your content it feels like your channel always has a video to one of my problems and I'm thankful for such resource

second at the end of this video you guys were in a bit of a hurry so I'm confused a bit at 54:20 he says its a bad idea to say "I'm just gonna use copper fill and stitching vias on signal layers" and at 1:01:30 eric says "thats why you don't wanna use copper pour you wanna use good return path engineering"
and you also said "I don't normally do copper fill" as it's unnecessary

however at 21:40 you talked about the need for stitching vias to minimize impedance between planes and eliminate long resonating cavities

so I'm confused cause this two statement seem opposite to me

does this mean it's a bad idea to use copper fills on excess spaces in the signal layers in general? if so I didn't understand why given the need to eliminate those cavities

or is he just talking about the difference between not using ground reference planes at all in the 2 layer case ?

sry I'm confused I would appreciate your thought on this

thanks

QDrives , 04-10-2026, 01:59 PM

At 54:20 it is about flooding signals layers and 21:40 is about plane layers.

But Eric Bogatin is a little simplistic in the 54:20 part.
1) Compares a terrible design Arduino Uno with a proper designed board. The near field noise it not so much due to flooding the top (signal) but the broken up bottom, lack of stiching vias and net antennas.
2) He also forgets that copper balancing is important too.

As for 'just' flooding copper on a signal layer thinking it will make things better -- yes, he is correct on that point. You need to know what you are doing.

Susano , 04-10-2026, 05:53 PM

As I understand till now is that
you need to be be careful about pours as a seemingly floating copper regions increase coupling between signals traces

This means I need to be careful about pouring 3.3V in signal layers ?
Since it would (from the signal pov) be a floating plane and in return help in increasing coupling and crosstalk even more between signals traces
did I get that right ?

QDrives , 04-11-2026, 12:08 AM

Correct.
But the net assigned to a polygon does not make it more or less susceptable to crosstalk and emitting that. Can the energy go back to the source.
In your rules, just increase the clearance to polygons.

Susano , 04-11-2026, 02:27 AM

Yes I get it now
Thanks a lot @QDrives you've been a huge help
God bless you