FEDEVEL
Platform forum

Sniper2 , 01-05-2025, 10:01 AM

So many chips have a thermal pad and the commandeered footprint has vias in it.
If i dont want to use caped and filled vias haw large can i make them?
Most often i see 0.2mm in the datasheet i was wandering would 0.25 or 0.3mm be ok? as in not that much solder will drain out of them?
Asking since if i am forced to use that small via type for a chip i raise the manufacture cost a lot on some board houses. (and then i am sort of forced to take advantage of that tiny drill in normal vias too)
I was thinking of puting some larger vias like 0.3mm drill instead of .2mm.
Can anyone tell me please how stuff works in practice or some extra recomandations?

Robert Feranec , 01-05-2025, 11:31 AM

I often use 0.3mm hole under exposed pad, no one reported any problems with it from production

Sniper2 , 01-05-2025, 12:32 PM

Thx